In a high-speed A/D-converter, the response time of the comparator(s) must be extremely short. It is therefore desirable to have a simple comparator circuit in order to reduce its inherent propagation delay. However, simple comparator circuits typically have low accuracy due to comparator offset errors, which makes them unsuitable for high-resolution A/D converters.
Careful circuit and layout design is the first key to low-offset comparators. Mismatch is caused by random variations within the resolution of the manufacturing process. It is a well-known fact that small devices are more sensitive to these random errors, while increasing physical size improves matching [1]. However, a drawback of increasing the physical size of the components is that this usually leads to increased power dissipation. This is true both for scaling of passive components like capacitances, and for active components such as MOS transistors. Even when power dissipation is not an issue, there is a practical limit on the achievable accuracy. By studying the open literature, it seems that a carefully designed comparator may give a precision equivalent to 3–4 bits.
A widely used method to reduce the effect of comparator offset is to put a pre-amplifier in front of the comparator. Assuming that the offset of the pre-amplifier is significantly less than the comparator offset, the effect of the comparator offset is now attenuated by the gain of the pre-amplifier [1]. However, by adding a preamplifier, the response time of the comparator increases with the propagation delay of the pre-amplifier. This increase in response time will significantly reduce the attainable sampling rate.
It has been shown that redundancy can be used for digital correction of A/D sub-converter decision levels in pipeline A/D converters. One common approach is to let the signal range of each pipeline stage overlap the preceding stage by 1-b (i.e., a factor of two). Then the A/D sub-converters need only to be accurate to the stage resolution [2]. However, with the additional requirement of extremely short propagation delay in, for example high-speed pipeline A/D converters, even a 4 or 5-bit flash A/D converter is very difficult to implement. Therefore the manufacturing yield may become very low.
The influence of comparator offset can be reduced by changing the reference levels or by adding a “counter-offset” to the reference voltage. Two prior art solutions are described below. Both approaches alter the reference voltage actually applied to the comparator.
The “reference-tap” method described in [3] assumes that the random offset variation is larger than 1 LSB of the voltage reference ladder. By trying out a few of the neighboring voltage reference taps, the tap that gives the least offset can be found. While conceptually simple, this method has the drawback that offset can only be calibrated to within +/−1 LSB of the reference ladder. This may be enough for a stand-alone flash A/D converter, but when the flash A/D converter is used as a sub-converter, e.g. in a pipeline A/D converter, it is desirable to have a more accurate compensation of the comparator offsets, since a higher-than-necessary comparator accuracy improves the overall performance in many practical implementations.
The “counter-offset voltage” method described in [4, 5] deliberately applies a secondary offset voltage, Va, to balance out the inherent offset of the comparator circuit. A feedback-loop comprising an up/down counter and a switched capacitor network is used to search for, and apply, the appropriate secondary offset voltage. The drawback of this method is that the secondary offset voltage (or trim voltage), Va, which cancels the comparator offset is stored on a capacitor. Therefore the trim voltage needs to be periodically refreshed. In between such refresh instances, the stored voltage is sensitive to glitches, which may alter the stored voltage. The method is also sensitive to glitches during calibration, since switching transients may cause a faulty trim voltage to be stored and used for the duration of a whole refresh cycle.